This invention relates to a semiconductor integrated circuit device and to a fabrication process thereof, and more particularly, the invention relates to a technique which is effective when applied to a semiconductor integrated circuit device, which is fabricated by a process including a planarization step using the CMP (Chemical Mechanical Polishing) method.
To satisfy the continuing tendency to decrease the minimum processing size of a semiconductor integrated circuit device, in an exposure optical system, an increase in the performance of a stepper is required, which promotes a widening of the aperture size of a lens and a shortening of the exposure wave length. As a result, the focus depth of the exposure optical system decreases and even a slight unevenness on the surface to be processed becomes a problem. Therefore, the accurate planarization of the surface to be processed becomes an important technical objective for the device process. Furthermore, the above planarization does not aim at the easing of a stepped portion for the purpose of preventing a short cut of interconnections formed on the stepped portion, but is directed to a global planarization, in other words, a complete planarization.
As a surface planarization technique, there are a method of coating an SOG (Spin On Glass) film or a low-melting-point glass by melting it, a method of heat treatment through glass flow, a self planarization method adopting a surface reaction mechanism of CVD (Chemical Vapor Deposition) and the like. Owing to the surface conditions, to the heat treatment conditions being applied or to limitations in processing, in many cases, it is impossible to carry out complete planarization, that is, global planarization, using these methods. Therefore, the etchback and CMP processes are regarded as promising practical techniques which permit complete planarization.
As for the etchback process, the use of a photoresist as a sacrificial film, the use of an SOG film and the use of a self-planarization CVD film are known, but they are accompanied by such drawbacks as a complex procedure, a high cost and a lowering of the yield due to production of particles. The CMP process has, on the other hand, come to be regarded as an excellent process from an overall viewpoint, because, compared with the etchback process, it is more free from the above-described problems. Consequently, the CMP process is considered to be most promising as a practical technique for effecting complete planarization.
The CMP technique is described in, for example, Japanese Patent Application Laid-Open No. HEI 7-74175, U.S. Pat. No. 5,292,689 and "1996 Symposium on VLSI Technology Digest of Technical Papers, 158-159(1996)".